--Szydrowanie
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity encryption is
    Port ( data : in  STD_LOGIC_VECTOR (127 downto 0);
		key : in STD_LOGIC_VECTOR (255 downto 0);
		cipher : out  STD_LOGIC_VECTOR (127 downto 0));
end encryption;

architecture Behavioral of encryption is

component initialtransf is
    Port ( i : in  STD_LOGIC_VECTOR (127 downto 0);
		o : out  STD_LOGIC_VECTOR (127 downto 0));
end component initialtransf;

component finaltransf is
    Port ( i : in  STD_LOGIC_VECTOR (127 downto 0);
		o : out  STD_LOGIC_VECTOR (127 downto 0));
end component finaltransf;

component runda32 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		rdk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component runda32;

component runda1 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component runda1;

component runda2 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component runda2;

component runda3 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component runda3;

component runda4 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
	rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component runda4;

component runda5 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component runda5;

component runda6 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component runda6;

component runda7 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component runda7;

component runda8 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component runda8;

component key_schedule is
    Port ( user_key : in  STD_LOGIC_VECTOR (255 downto 0);
		k0 : out  STD_LOGIC_VECTOR (127 downto 0);
		k1 : out  STD_LOGIC_VECTOR (127 downto 0);
		k2 : out  STD_LOGIC_VECTOR (127 downto 0);
		k3 : out  STD_LOGIC_VECTOR (127 downto 0);
		k4 : out  STD_LOGIC_VECTOR (127 downto 0);
		k5 : out  STD_LOGIC_VECTOR (127 downto 0);
		k6 : out  STD_LOGIC_VECTOR (127 downto 0);
		k7 : out  STD_LOGIC_VECTOR (127 downto 0);
		k8 : out  STD_LOGIC_VECTOR (127 downto 0);
		k9 : out  STD_LOGIC_VECTOR (127 downto 0);
		k10 : out  STD_LOGIC_VECTOR (127 downto 0);
		k11 : out  STD_LOGIC_VECTOR (127 downto 0);
		k12 : out  STD_LOGIC_VECTOR (127 downto 0);
		k13 : out  STD_LOGIC_VECTOR (127 downto 0);
		k14 : out  STD_LOGIC_VECTOR (127 downto 0);
		k15 : out  STD_LOGIC_VECTOR (127 downto 0);
		k16 : out  STD_LOGIC_VECTOR (127 downto 0);
		k17 : out  STD_LOGIC_VECTOR (127 downto 0);
		k18 : out  STD_LOGIC_VECTOR (127 downto 0);
		k19 : out  STD_LOGIC_VECTOR (127 downto 0);
		k20 : out  STD_LOGIC_VECTOR (127 downto 0);
		k21 : out  STD_LOGIC_VECTOR (127 downto 0);
		k22 : out  STD_LOGIC_VECTOR (127 downto 0);
		k23 : out  STD_LOGIC_VECTOR (127 downto 0);
		k24 : out  STD_LOGIC_VECTOR (127 downto 0);
		k25 : out  STD_LOGIC_VECTOR (127 downto 0);
		k26 : out  STD_LOGIC_VECTOR (127 downto 0);
		k27 : out  STD_LOGIC_VECTOR (127 downto 0);
		k28 : out  STD_LOGIC_VECTOR (127 downto 0);
		k29 : out  STD_LOGIC_VECTOR (127 downto 0);
		k30 : out  STD_LOGIC_VECTOR (127 downto 0);
		k31 : out  STD_LOGIC_VECTOR (127 downto 0);
		k32 : out  STD_LOGIC_VECTOR (127 downto 0));
end component key_schedule;

signal n1, n0, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, Kl0, Kl1, Kl2, Kl3, Kl4, Kl5, Kl6, Kl7, Kl8, Kl9, Kl10, Kl11, Kl12, Kl13, Kl14, Kl15, Kl16, Kl17, Kl18, Kl19, Kl20, Kl21, Kl22, Kl23, Kl24, Kl25, Kl26, Kl27, Kl28, Kl29, Kl30, Kl31, Kl32 : STD_LOGIC_VECTOR (127 downto 0);
begin
--szykowanie kluczy
klucze: key_schedule port map (key, KL0, KL1, KL2, KL3, KL4, KL5, KL6, KL7, KL8, KL9, KL10, KL11, KL12, KL13, KL14, KL15, KL16, KL17, KL18, KL19, KL20, KL21, KL22, KL23, KL24, KL25, KL26, KL27, KL28, KL29, KL30, KL31, KL32);
--poczatkowa permutacja
inperm: initialtransf port map (data, n1);
--rundy 1-31
r1: runda1 port map (n1, KL0, n2);
r2: runda2 port map (n2, KL1, n3);
r3: runda3 port map (n3, KL2, n4);
r4: runda4 port map (n4, KL3, n5);
r5: runda5 port map (n5, KL4, n6);
r6: runda6 port map (n6, KL5, n7);
r7: runda7 port map (n7, KL6, n8);
r8: runda8 port map (n8, KL7, n9);
r9: runda1 port map (n9, KL8, n10);
r10: runda2 port map (n10, KL9, n11);
r11: runda3 port map (n11, KL10, n12);
r12: runda4 port map (n12, KL11, n13);
r13: runda5 port map (n13, KL12, n14);
r14: runda6 port map (n14, KL13, n15);
r15: runda7 port map (n15, KL14, n16);
r16: runda8 port map (n16, KL15, n17);
r17: runda1 port map (n17, KL16, n18);
r18: runda2 port map (n18, KL17, n19);
r19: runda3 port map (n19, KL18, n20);
r20: runda4 port map (n20, KL19, n21);
r21: runda5 port map (n21, KL20, n22);
r22: runda6 port map (n22, KL21, n23);
r23: runda7 port map (n23, KL22, n24);
r24: runda8 port map (n24, KL23, n25);
r25: runda1 port map (n25, KL24, n26);
r26: runda2 port map (n26, KL25, n27);
r27: runda3 port map (n27, KL26, n28);
r28: runda4 port map (n28, KL27, n29);
r29: runda5 port map (n29, KL28, n30);
r30: runda6 port map (n30, KL29, n31);
r31: runda7 port map (n31, KL30, n32);
--runda 32 gdzie zamiast lineartransf mamy XOR z kluczem dodatkowym
r32: runda32 port map (n32, KL31, KL32,n0);
--final transformation
finperm: finaltransf port map (n0,cipher);
end Behavioral;